<div><strong>Anthriq</strong> is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical, deterministic workloads.</div><div>Our infrastructure is designed around one principle: the signal should never be the bottleneck. General-purpose processors — CPUs, GPUs, DSPs — were not built for this class of problems. They approximate determinism. We build it into the architecture.</div><div>Anthriq Silicon is our ground-up effort to build a new compute category.</div><div><br></div><div>Read More About Anthriq Silicon Program here: <a href="https://dataroom.anthriq.com/xL2dwHtZS7" rel="noopener noreferrer" target="_blank">https://dataroom.anthriq.com/xL2dwHtZS7</a></div>

Anthriq

<p><b>About the company:</b><b></b></p>
<p>Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical, deterministic workloads.</p>
<p>Our infrastructure is designed around one principle: the signal should never be the bottleneck. General-purpose processors — CPUs, GPUs, DSPs — were not built for this class of problems. They approximate determinism. We built it in by architecture.</p>
<p>Anthriq Silicon is our ground-up effort to build a new compute category.</p>
<p><strong>Key responsibilities</strong></p>
<ul>
<li>Architect UVM testbenches for memory-subsystem wrappers, credit-based flow control, and multi-channel DMA.</li>
<li>Develop packet-level protocol checkers, retry-buffer FSM monitors, and error-injection benches for a custom die-to-die link<br>layer, incl. cross-die fail-stop.</li>
<li>Verify hardware synchronization barriers and multi-client arbitration scoreboards.</li>
<li>Own test-plan execution, mentor junior engineers, drive block coverage to 100%.</li>
</ul>
<p><strong>Must-have skills</strong></p>
<ul>
<li>8+ years verifying memory controllers (LPDDR4/5/5X) or high-speed interconnect protocols and DMA engines.</li>
<li>Credit-based flow control, arbitration, memory-map region protection.</li>
<li>UVM architecture, constrained-random stimulus, functional-coverage modeling.</li>
<li>Link-layer packetization, retry, framing FSM verification.</li>
<li>Clock-Domain-Crossing (CDC) verification.</li>
</ul>
<p><strong>Nice-to-have</strong></p>
<ul>
<li>Multi-die / die-to-die (UCIe-class or proprietary) link experience.</li>
<li>PHY-to-MAC protocol simulation.</li>
</ul>
<p><strong>Target EDA tools: </strong>Cadence Xcelium, vManager, Indago</p>