<div><strong>Anthriq</strong> is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical, deterministic workloads.</div><div>Our infrastructure is designed around one principle: the signal should never be the bottleneck. General-purpose processors — CPUs, GPUs, DSPs — were not built for this class of problems. They approximate determinism. We build it into the architecture.</div><div>Anthriq Silicon is our ground-up effort to build a new compute category.</div><div><br></div><div>Read More About Anthriq Silicon Program here: <a href="https://dataroom.anthriq.com/xL2dwHtZS7" rel="noopener noreferrer" target="_blank">https://dataroom.anthriq.com/xL2dwHtZS7</a></div>

Anthriq

<p><b>About the company:</b><b></b></p>
<p>Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical, deterministic workloads.</p>
<p>Our infrastructure is designed around one principle: the signal should never be the bottleneck. General-purpose processors — CPUs, GPUs, DSPs — were not built for this class of problems. They approximate determinism. We built it in by architecture.</p>
<p>Anthriq Silicon is our ground-up effort to build a new compute category.</p>
<p><br><strong>Key responsibilities</strong></p>
<ul>
<li>Architect multi-agent UVM environments for a wide-issue VLIW pipeline (fetch, decode, hazard detection, execution units, in-<br>flight credit model).</li>
<li>Build equivalence scoreboards: SystemVerilog RTL vs. C/C++ cycle-accurate ISS, integer and IEEE-754 FP.</li>
<li>Develop constrained-random assembly generators for 100% ISA and register-file coverage across a large custom opcode<br>space.</li>
<li>Write SVA and drive formal property verification for arithmetic pipelines (fixed/float FMA, matrix multipliers, CORDIC,<br>dividers).</li>
<li>Verify a compiler/hardware worst-case-timing contract (measured vs. claimed latency).</li>
<li>Execute and debug block-level SDF back-annotated GLS.</li>
</ul>
<p><strong>Must-have skills:<br></strong></p>
<ul>
<li>5+ years verifying processor cores (VLIW, SIMD, DSP, or custom RISC-V vector extensions).</li>
<li>Advanced SystemVerilog, UVM, SVA.</li>
<li>IEEE-754 floating-point AND fixed-point arithmetic-pipeline verification; matrix math, FFT/CORDIC.</li>
<li>Proven 100% functional-coverage closure on complex IP.</li>
</ul>
<p><strong>Nice to Have:</strong></p>
<ul>
<li>C/C++ reference modeling.</li>
<li>Formal tools / proof convergence.</li>
<li>WCET / timing-contract verification</li>
<li>Target EDA tools: Cadence Xcelium, JasperGold, vManager</li>
</ul>
<p></p>