<div><strong>Anthriq</strong> is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical, deterministic workloads.</div><div>Our infrastructure is designed around one principle: the signal should never be the bottleneck. General-purpose processors — CPUs, GPUs, DSPs — were not built for this class of problems. They approximate determinism. We build it into the architecture.</div><div>Anthriq Silicon is our ground-up effort to build a new compute category.</div><div><br></div><div>Read More About Anthriq Silicon Program here: <a href="https://dataroom.anthriq.com/xL2dwHtZS7" rel="noopener noreferrer" target="_blank">https://dataroom.anthriq.com/xL2dwHtZS7</a></div>

Anthriq

<p><strong>About Company</strong></p>
<p>Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical workloads.<br><br><strong>About the Role</strong></p>
<p>We're looking for a <strong>Senior&nbsp;Compiler Engineer </strong>to own the system software stack that sits between Anthriq Silicon and the applications running on it, compiler infrastructure, low-level firmware, and real-time signal compute pipelines with sub-millisecond latency requirements.&nbsp;The ideal candidate has shipped production LLVM compiler pipelines at a semiconductor company, has hands-on embedded bring-up experience, and brings formal verification rigour to safety-critical real-time systems.<br><br><strong>What You'll Do</strong></p>
<ul>
<li>Own custom LLVM backend passes, instruction selection (SelectionDAG / GlobalISel), MIR-level optimizations, and register allocator improvements for real-time execution paths</li>
<li>Build compiler fuzzing infrastructure and formal verification frameworks (Alive2 / SMT), with zero miscompilations in safety-critical pipelines</li>
<li>Implement device drivers and protocol stacks (USB, SPI, I2C, UART, PCIe, CAN) for real-time biosignal acquisition</li>
<li>Work with Linux kernel subsystems, RT-PREEMPT, SCHED_FIFO, and kernel modules for deterministic biosignal scheduling</li>
<li>Profile and optimize across CPU / GPU architectures using perf, gdb, Nsight, rocprof, valgrind, and eBPF</li>
<li>Author SRDs and SDDs; lead design reviews and mentor engineers across C++, LLVM, and embedded systems</li>
<li>Collaborate with hardware teams on silicon bring-up and BSP development ahead of tape-out</li>
</ul>
<p><strong>What We're Looking For</strong></p>
<ul>
<li>10+ years in system-level C++ spanning GPU compiler engineering, embedded firmware, and kernel-adjacent work</li>
<li>Deep LLVM expertise: SelectionDAG, GlobalISel, MIR, register allocator, TableGen, custom pass development.</li>
<li>GPU programming: CUDA / HIP; GPU execution model expertise (warp scheduling, register files, occupancy)</li>
<li>Compiler correctness: fuzzing harnesses, formal verification (Alive2, SMT/SAT), differential testing</li>
<li>Advanced debugging: gdb, Lauterbach JTAG, logic/protocol analyzers, AddressSanitizer</li>
<li>M.E. / M.S. in CS, Embedded Systems, or related field</li>
</ul>
<p><strong>Bonus</strong></p>
<ul>
<li>FPGA design (Verilog / VHDL) and assembly-level programming (PTX, GCN, SASS, x86, 8051)</li>
</ul>
<p></p>