<div>Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical, deterministic workloads.</div><div>Our infrastructure is designed around one principle: the signal should never be the bottleneck. General-purpose processors — CPUs, GPUs, DSPs — were not built for this class of problems. They approximate determinism. We build it into the architecture.</div><div>Anthriq Silicon is our ground-up effort to build a new compute category.</div><div> </div><div>Read More About Anthriq Silicon Program here: <a href="https://dataroom.anthriq.com/xL2dwHtZS7" rel="noopener noreferrer" target="_blank">https://dataroom.anthriq.com/xL2dwHtZS7</a></div>

Anthriq

About the company:
Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical workloads.
Anthriq Silicon is our ground-up effort to build a new compute category. Read More About Anthriq Silicon Program here: anthriq.com/silicon
 About the Role We are building a compute-heavy multi-core vector processor with a custom ISA. &nbsp;You will own synthesis runs, critical path analysis, power estimation, and PPA (Power/Performance/Area) tracking. You are the early warning system — finding timing and power problems months before tapeout. Responsibilities ● Run trial synthesis continuously from early RTL (not waiting for RTL freeze) ● Identify and resolve critical timing paths before they become tapeout blockers ● Optimize high-fan-out logic: comparator arrays, mux trees, crossbar switching ● Run power estimation from simulation switching activity — track TDP vs budget ● Maintain a PPA dashboard: weekly reports on frequency achieved, power breakdown by block, area breakdown ● Analyze clock gating eectiveness (dynamic power reduction) ● Refine SDC constraints based on synthesis results (false paths, multicycle paths) ● Assist RTL Lead with timing closure strategy Requirements ● 5+ years RTL design + synthesis experience (must understand both sides) ● Synthesis tools: Design Compiler or Genus ● Static timing analysis: PrimeTime or Tempus ● Power analysis: switching activity annotation, gate-level power estimation ● Strong scripting (Tcl for EDA tools, Python for reporting and dashboards) ● Ability to read and optimize gate-level netlists Nice to Have ● Experience with high-frequency ASIC design (&gt;500 MHz) ● Floorplan-aware synthesis (Fusion Compiler or physical-aware DC) ● IR drop analysis (Voltus, RedHawk) ● Process node experience at advanced nodes (28nm class or below)