<div>Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical, deterministic workloads.</div><div>Our infrastructure is designed around one principle: the signal should never be the bottleneck. General-purpose processors — CPUs, GPUs, DSPs — were not built for this class of problems. They approximate determinism. We build it into the architecture.</div><div>Anthriq Silicon is our ground-up effort to build a new compute category.</div><div> </div><div>Read More About Anthriq Silicon Program here: <a href="https://dataroom.anthriq.com/xL2dwHtZS7" rel="noopener noreferrer" target="_blank">https://dataroom.anthriq.com/xL2dwHtZS7</a></div>

Anthriq

About the company:
Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical workloads.
Anthriq Silicon is our ground-up effort to build a new compute category. Read More About Anthriq Silicon Program here: anthriq.com/silicon About the Role We are building a compute-heavy multi-core vector processor with a custom ISA. You will implement the on-chip interconnect fabric, the high-speed serial interfaces, the PCIe endpoint, and the inter-core synchronization engine. Responsibilities ● Implement the on-chip network: a multi-stage switch fabric with credit-based flow control and virtual channels ● Build the high-speed serial interface: frame encoding/decoding, CRC, link training, automatic retry (ARQ) ● Implement a PCIe Gen3 x16 endpoint: DMA engines, BAR decode, MSI-X interrupt controller, PHY interface selection ● Build the inter-core synchronization engine: barrier logic, signal routing, multi-channel event distribution ● Design and verify all clock domain crossings (asyncFIFOs, gray-code pointers, synchronizers) ● Implement protocol-level compliance (high-speed serial framing, PCIe TLP handling) Requirements ● 5+ years RTL design in SystemVerilog ● Network-on-chip or crossbar/switch fabric design ● High-speed SerDes experience (8b/10b encoding, CRC, link-layer framing) ● PCIe endpoint design or integration (Gen3 or later) ● Clock domain crossing (CDC) design — async FIFOs, gray-code, 2FF synchronizers ● Credit-based flow control Nice to Have ● Multi-stage switch network design ● JESD204B/C experience ● DMA engine design (scaer-gather, descriptor chains) ● Formal verification of protocol properties