<div>Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical, deterministic workloads.</div><div>Our infrastructure is designed around one principle: the signal should never be the bottleneck. General-purpose processors — CPUs, GPUs, DSPs — were not built for this class of problems. They approximate determinism. We build it into the architecture.</div><div>Anthriq Silicon is our ground-up effort to build a new compute category.</div><div> </div><div>Read More About Anthriq Silicon Program here: <a href="https://dataroom.anthriq.com/xL2dwHtZS7" rel="noopener noreferrer" target="_blank">https://dataroom.anthriq.com/xL2dwHtZS7</a></div>

Anthriq

About Anthriq
Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical workloads.
Anthriq Silicon is our ground-up effort to build a new compute category — a custom ISA, a frontier signal-processing chip, and a full toolchain designed alongside the silicon. Every layer is being built, not assembled. → anthriq.com/silicon About the Role
We're building a compute-heavy multi-core vector processor with a custom ISA, and we're hiring RTL engineers across multiple domains. You don't need to cover everything —we want engineers who go deep in at least one area and can grow into adjacent ones.
When you apply, tell us your primary strength:
<ul>
<li>Datapath — execution units, register files, floating-point arithmetic</li>
<li>Fabric &amp; Interconnect — on-chip networks, PCIe, high-speed serial, CDC</li>
<li>Pipeline Control — scoreboards, dispatch logic, DMA, CSR</li>
<li>Orchestration &amp; Integration — SoC top-level, AXI bus fabric, system controller</li>
<li>Peripherals &amp; Security — DDR controller, secure boot, JTAG, trace</li>
<li>Performance &amp; PPA — synthesis, timing closure, power analysis</li>
</ul>
What You'll Work On
Depending on your area:
Datapath — Implement execution units (integer, FP, fixed-point, complex), multi-port register files, bypass/forwarding networks, IEEE 754-compliant FP datapaths, and critical arithmetic paths (carry-save adders, Wallace trees, Booth multipliers).
Fabric &amp; Interconnect — Build a multi-stage switch fabric with credit-based flow control, high-speed serial interfaces (8b/10b, CRC, ARQ), PCIe Gen3 x16 endpoint, and all clock domain crossing logic.
Pipeline Control — Implement the instruction scoreboard, dispatch logic, pipeline drain/flush FSMs, multi-channel DMA controller, AXI-Stream IO FIFOs, and CSR register file.
Orchestration &amp; Integration — Build the RISC-V-based system management controller, AXI4-Lite multi-master bus infrastructure, and own top-level chip integration across all blocks, clocks, and resets.
Peripherals &amp; Security — Integrate DDR4 memory controller, implement silicon root-of-trust/secure boot/key management, build JTAG debug controller (IEEE 1149.1), and trace aggregation unit.
Performance &amp; PPA — Run synthesis continuously from early RTL, identify and resolve critical timing paths, run power estimation from switching activity, and maintain weekly PPA dashboards with Tcl/Python scripts.
Requirements
All areas:
<ul>
<li>5+ years RTL design in SystemVerilog</li>
<li>Strong digital design fundamentals, you design from spec, not from templates</li>
<li>Comfortable in a small team where ownership is real and total</li>
</ul>
Why This Role
This is not an integration job. You write RTL that ships in silicon. You own your block end-to-end from spec to synthesis to verification sign-off. The team is small, the problem is genuinely hard, and the work is built to last.