<div><strong>Anthriq</strong> is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical, deterministic workloads.</div><div>Our infrastructure is designed around one principle: the signal should never be the bottleneck. General-purpose processors — CPUs, GPUs, DSPs — were not built for this class of problems. They approximate determinism. We build it into the architecture.</div><div>Anthriq Silicon is our ground-up effort to build a new compute category.</div><div><br></div><div>Read More About Anthriq Silicon Program here: <a href="https://dataroom.anthriq.com/xL2dwHtZS7" rel="noopener noreferrer" target="_blank">https://dataroom.anthriq.com/xL2dwHtZS7</a></div>

Anthriq

<p><strong>About the Role</strong></p>
<p>We are building high-performance, compact electronic systems that depend on tightly engineered PCBs — multi-layer, small form-factor boards carrying high-speed digital, analog, mixed-signal, and high-power interfaces. You will own schematic capture and layout for these boards, working closely with hardware, firmware, mechanical, and manufacturing teams to take designs from concept through fabrication, assembly, and bring-up.</p>
<p><strong>Responsibilities</strong></p>
<ul>
<li>Design dense, small form-factor multi-layer PCB layouts for analog, digital, mixed-signal, and high-power subsystems.</li>
<li>Implement High-Density Interconnect (HDI) layout strategies, including microvias, blind/buried vias, via-in-pad, and fine-pitch BGA escape routing.</li>
<li>Apply EMI/EMC compliance considerations during layout, including grounding strategy, shielding, filtering, and trace/plane placement to minimize emissions and susceptibility.</li>
<li>Perform component selection, footprint creation, and BOM management in line with cost, availability, and performance targets.</li>
<li>Route high-speed signals while managing impedance control, length matching, differential pairs, and crosstalk.</li>
<li>Design high-power boards, including power converter stages, high-current traces/planes, copper pour/thermal relief strategies, and creepage/clearance for voltage isolation.</li>
<li>Apply signal integrity and power integrity best practices, including decoupling strategy, stack-up definition, plane partitioning, and return-path management.</li>
<li>Lead Design for Manufacturability (DFM), Design for Assembly (DFA), and Design for Test (DFT) reviews across the design cycle with fabrication and CM partners.</li>
<li>Own manufacturability sign-off by resolving DFM/DFA/DFT findings before release, including annotating fabrication drawings, assembly drawings, and Gerber/ODB++ outputs.</li>
<li>Coordinate with mechanical engineering on board outlines, 3D STEP clearances, tight form-factor constraints, connector placement, enclosure fit, and thermal management.</li>
<li>Manage Engineering Change Orders (ECOs) and maintain design files using Altium version control workflows (Altium 365 / Git / SVN).</li>
<li>Work with the verification team to support bring-up, debug, and rework of prototype boards using standard lab equipment.</li>
</ul>
<p><strong>Requirements</strong></p>
<ul>
<li>3–4 years of hands-on experience in PCB schematic capture, footprint creation, and multi-layer layout.</li>
<li>Primary proficiency in <strong>Altium Designer</strong> for end-to-end schematic capture and PCB layout.</li>
<li>Working knowledge of <strong>Cadence Allegro PCB Designer</strong> for basic layout modifications, review, or routing tasks.</li>
<li>Demonstrated hands-on experience designing <strong>High-Density Interconnect (HDI) PCBs</strong> (laser-drilled microvias, blind/buried vias, via-in-pad plated over, fine-pitch BGA fanouts).</li>
<li>Proven track record designing <strong>small form-factor / space-constrained boards</strong> with tight component placement and strict Z-height/mechanical limits.</li>
<li>Experience managing PCB design files and schematics using version control systems (Altium 365 workspace, Git, SVN, or similar ECAD data management workflows).</li>
<li>Experience with Gerber/ODB++ and manufacturing output verification using CAM tools (CAM350, Valor NPI, or native CAM viewers).</li>
<li>Demonstrated experience designing high-speed digital (impedance-controlled routing, length matching) and high-power/power delivery boards.</li>
<li>Solid track record of applying DFM, DFA, and DFT principles to complex, dense production designs.</li>
<li>Working knowledge of multi-layer stack-up design, layer mapping, and power/ground plane strategies.</li>
<li>Familiarity with industry standards (IPC-2221, IPC-6012, IPC-A-610, IPC-2226 for HDI) for design, fabrication, and assembly.</li>
<li>Ability to read datasheets and application notes to translate constraints into layout rules.</li>
<li>Comfortable using basic lab equipment (oscilloscopes, multimeters, power supplies) for board bring-up and debug support.</li>
</ul>
<p><strong>Nice to Have</strong></p>
<ul>
<li>Advanced schematic capture in OrCAD Capture or advanced layout capabilities in Cadence Allegro.</li>
<li>Experience routing complex multi-gigabit interfaces (DDR3/4/5, PCIe, USB3, SerDes).</li>
<li>Exposure to Rigid-Flex PCB layout and dynamic flex stack-ups.</li>
<li>Exposure to SI/PI simulation tools (HyperLynx, SIwave, ADS) or thermal simulation.</li>
<li>Direct experience collaborating with contract manufacturers (CMs) during NPI ramp for HDI production.</li>
<li>Basic understanding of RF layout practices and controlled-impedance RF trace routing.</li>
<li>Familiarity with project tracking and documentation platforms (Jira, Confluence, Notion).</li>
</ul>
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