<div>Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical, deterministic workloads.</div><div>Our infrastructure is designed around one principle: the signal should never be the bottleneck. General-purpose processors — CPUs, GPUs, DSPs — were not built for this class of problems. They approximate determinism. We build it into the architecture.</div><div>Anthriq Silicon is our ground-up effort to build a new compute category.</div><div> </div><div>Read More About Anthriq Silicon Program here: <a href="https://dataroom.anthriq.com/xL2dwHtZS7" rel="noopener noreferrer" target="_blank">https://dataroom.anthriq.com/xL2dwHtZS7</a></div>

Anthriq

About Us
Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems.
Anthriq Silicon is our ground-up effort to build a new compute category. Read more about the Anthriq Silicon Program here: anthriq.com/silicon About the Role
We are installing a Cadence Palladium Z3 emulation platform, and we are looking for the engineer who will own it end to end: install, the compile and debug flow, in-circuit bring-up with real hardware, hardware/software co-verification, and the day-to-day operation of the platform as a shared resource across our design, verification, firmware, and software teams.
This is a greenfield role and the first emulation hire at the company. There is no existing flow to inherit and no one above you who has done this here before. You will define how emulation works at Anthriq, hold the standard that keeps RTL emulation-ready, and build a team who will run the platform with you. The role runs from pre-silicon verification through to first-silicon bring-up in the lab. Responsibilities
Platform
<ul>
<li>Drive installation through to first successful full-chip compile</li>
<li>Own the compile flow end to end — partitioning, capacity allocation, compile turnaround time, and incremental compile strategy</li>
<li>Own capacity planning and platform roadmap</li>
</ul>
Design enablement
<ul>
<li>Define and enforce the emulation-readiness standard for RTL: clock and reset structure, gated clocks, memory inference and mapping, initialization and X-handling, and synthesizable coding rules</li>
<li>Work directly with the design team so RTL arrives emulation-clean</li>
</ul>
In-circuit and co-verification
<ul>
<li>Bring up in-circuit targets against real hardware — converters, high-speed serial links, host attach, and networking interfaces — including rate adaptation, clock domain crossing to physical devices, and the lab debug that follows</li>
<li>Build the flow that lets firmware engineers boot and debug embedded firmware on the emulator, and support software and compiler teams running realistic workloads pre-silicon</li>
<li>Model the memory subsystem and validate its behaviour under realistic traffic</li>
</ul>
Operations and delivery
<ul>
<li>Run emulation as an internal service: allocate capacity across teams, arbitrate resource planning, and keep utilisation optimum</li>
<li>Build the regression, automation, and triage infrastructure so failures reach the right engineer with the right debug data attached</li>
<li>Own gate-level and power-aware emulation ahead of tapeout, and convert the emulation suite into the silicon bring-up suite afterwards</li>
</ul>
Requirements
<ul>
<li>8+ years in ASIC/SoC verification, including at least 4 years hands-on with a hardware emulation platform. Cadence Palladium, Synopsys ZeBu, and Siemens Veloce all count — we care that you have done this work</li>
<li>You have brought up an emulation platform from near-zero at least once: defined the flow, made the first full-chip compile work, and got other teams using it</li>
<li>Hands-on in-circuit emulation experience. You have connected real hardware to an emulated design and debugged it when it did not work</li>
<li>Strong RTL literacy in SystemVerilog and Verilog — enough to read another engineer's design, identify what will not emulate, and propose the fix</li>
<li>Deep debug practice: waveform capture at scale, trigger and trace strategy, save-and-restore, force and deposit, and the discipline to correlate emulation failures back to simulation</li>
<li>Hardware/software co-verification experience — firmware or bare-metal bring-up on emulation, debugger attach, and boot flows</li>
<li>Strong scripting in Python and TCL, with ownership of build files, job scheduling, and regression automation</li>
<li>At least one silicon tapeout where you were accountable for a verification deliverable</li>
<li>The judgment and communication to ration a scarce shared resource across competing teams, and to explain the decision</li>
</ul>
Strongly preferred
<ul>
<li>Prior Palladium experience, or familiarity with the wider Cadence verification toolchain</li>
<li>Speed bridges or protocol bridges for in-circuit use</li>
<li>SCE-MI or transactor-based testbench architecture, and accelerated verification IP</li>
<li>UVM fluency — you will constantly be deciding what belongs in simulation and what belongs on the emulator</li>
<li>Embedded processor bring-up; high-speed serial, converter, or networking interfaces</li>
<li>Low-power emulation (UPF) and dynamic power analysis</li>
<li>FPGA prototyping — Protium, HAPS, or custom</li>
<li>DSP, radar, imaging, or biosignal domain exposure - good to have</li>
</ul>