<div><strong>Anthriq</strong> is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical, deterministic workloads.</div><div>Our infrastructure is designed around one principle: the signal should never be the bottleneck. General-purpose processors — CPUs, GPUs, DSPs — were not built for this class of problems. They approximate determinism. We build it into the architecture.</div><div>Anthriq Silicon is our ground-up effort to build a new compute category.</div><div><br></div><div>Read More About Anthriq Silicon Program here: <a href="https://dataroom.anthriq.com/xL2dwHtZS7" rel="noopener noreferrer" target="_blank">https://dataroom.anthriq.com/xL2dwHtZS7</a></div>

Anthriq

<p><b>About the company:</b><b></b></p>
<p>Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical, deterministic workloads.</p>
<p>Our infrastructure is designed around one principle: the signal should never be the bottleneck. General-purpose processors — CPUs, GPUs, DSPs — were not built for this class of problems. They approximate determinism. We built it in by architecture.</p>
<p>Anthriq Silicon is our ground-up effort to build a new compute category.</p>
<p><strong>About the Role:</strong><br>We're hiring a protocol verification authority to own sign-off on high-speed I/O interfaces for a next-gen SoC — PCIe Gen5, 32G+ SerDes, LPDDR5X, and Ethernet 25G-KR. This is an audit/authority role: you'll validate compliance logs, link-training, and PHY behavior delivered by our silicon partner before it clears sign-off.</p>
<p></p>
<p><strong>Key responsibilities</strong></p>
<ul>
<li>Audit and sign off PCIe Gen5 LTSSM logs, PIPE-interface timing, route/test cases.</li>
<li>Validate LPDDR5X PHY initialization, training algorithms, PHY-to-controller handshakes.</li>
<li>Audit 32G+ SerDes equalization, framing FSMs, lane-reversal/polarity, and JESD204B/C deterministic-latency alignment.</li>
<li>Audit Ethernet 25G-KR MAC/PCS.</li>
<li>Configure, run, and debug commercial VIP for high-speed protocols.</li>
</ul>
<p><strong>Must-have skills</strong></p>
<ul>
<li>8+ years in high-speed I/O protocol verification (PCIe Gen4/Gen5, LPDDR4/5X, 28G/32G/56G SerDes).</li>
<li>JESD204B/C converter-interface verification with deterministic latency.</li>
<li>Ethernet MAC/PCS (25G-KR / backplane).</li>
<li>Commercial VIP integration and debug; strong protocol waveform analysis.</li>
</ul>
<p><strong>Nice-to-have</strong></p>
<ul>
<li>TSMC 7nm/5nm PHY integration tuning.</li>
<li>Performance benchmarking under I/O congestion.</li>
<li>Target EDA tools: Cadence VIPs (PCIe, LPDDR, SerDes, JESD, Ethernet), Xcelium, Indago</li>
</ul>